%0 Conference Paper %1 conf/slip/HeDHG09 %A He, Xu %A Dong, Sheqin %A Hong, Xianlong %A Goto, Satoshi %B SLIP %D 2009 %E Cheng, Chung-Kuan %E Reda, Sherief %I ACM %K dblp %P 99-104 %T Integrated interlayer via planning and pin assignment for 3D ICs. %U http://dblp.uni-trier.de/db/conf/slip/slip2009.html#HeDHG09 %@ 978-1-60558-576-5

@inproceedings{conf/slip/HeDHG09, added-at = {2018-11-06T00:00:00.000+0100}, author = {He, Xu and Dong, Sheqin and Hong, Xianlong and Goto, Satoshi}, biburl = {https://www.bibsonomy.org/bibtex/26dc151a4d8f83d051d11a65293ac07af/dblp}, booktitle = {SLIP}, crossref = {conf/slip/2009}, editor = {Cheng, Chung-Kuan and Reda, Sherief}, ee = {https://doi.org/10.1145/1572471.1572488}, interhash = {301f2280b9f3a12d46361e46346dad09}, intrahash = {6dc151a4d8f83d051d11a65293ac07af}, isbn = {978-1-60558-576-5}, keywords = {dblp}, pages = {99-104}, publisher = {ACM}, timestamp = {2018-11-07T15:05:39.000+0100}, title = {Integrated interlayer via planning and pin assignment for 3D ICs.}, url = {http://dblp.uni-trier.de/db/conf/slip/slip2009.html#HeDHG09}, year = 2009 }