%0 Conference Paper %1 conf/dac/TsengLYJTLS16 %A Tseng, Tsun-Ming %A Li, Bing %A Yeh, Ching-Feng %A Jhan, Hsiang-Chieh %A Tsai, Zuo-Min %A Lin, Mark Po-Hung %A Schlichtmann, Ulf %B DAC %D 2016 %I ACM %K dblp %P 101:1-101:6 %T Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing. %U http://dblp.uni-trier.de/db/conf/dac/dac2016.html#TsengLYJTLS16 %@ 978-1-4503-4236-0

@inproceedings{conf/dac/TsengLYJTLS16, added-at = {2023-11-12T00:00:00.000+0100}, author = {Tseng, Tsun-Ming and Li, Bing and Yeh, Ching-Feng and Jhan, Hsiang-Chieh and Tsai, Zuo-Min and Lin, Mark Po-Hung and Schlichtmann, Ulf}, biburl = {https://www.bibsonomy.org/bibtex/206a2740540e6e197a15917568bc2c608/dblp}, booktitle = {DAC}, crossref = {conf/dac/2016}, ee = {https://doi.org/10.1145/2897937.2898052}, interhash = {312784b4eb191c6d801547172434791a}, intrahash = {06a2740540e6e197a15917568bc2c608}, isbn = {978-1-4503-4236-0}, keywords = {dblp}, pages = {101:1-101:6}, publisher = {ACM}, timestamp = {2024-04-10T06:55:10.000+0200}, title = {Novel CMOS RFIC layout generation with concurrent device placement and fixed-length microstrip routing.}, url = {http://dblp.uni-trier.de/db/conf/dac/dac2016.html#TsengLYJTLS16}, year = 2016 }