%0 Journal Article %1 journals/jsa/XuJW24 %A Xu, Qing %A Jiang, Qisheng %A Wang, Chundong %D 2024 %J J. Syst. Archit. %K dblp %P 103109 %T Caiti: I/O transit caching for persistent memory-based block device. %U http://dblp.uni-trier.de/db/journals/jsa/jsa150.html#XuJW24 %V 150

@article{journals/jsa/XuJW24, added-at = {2024-10-06T00:00:00.000+0200}, author = {Xu, Qing and Jiang, Qisheng and Wang, Chundong}, biburl = {https://www.bibsonomy.org/bibtex/2d5957f7996a6767683e2bea46e87b8d0/dblp}, ee = {https://doi.org/10.1016/j.sysarc.2024.103109}, interhash = {32b2160bd4e7fceae2861d279e65347c}, intrahash = {d5957f7996a6767683e2bea46e87b8d0}, journal = {J. Syst. Archit.}, keywords = {dblp}, pages = 103109, timestamp = {2024-10-07T07:16:06.000+0200}, title = {Caiti: I/O transit caching for persistent memory-based block device.}, url = {http://dblp.uni-trier.de/db/journals/jsa/jsa150.html#XuJW24}, volume = 150, year = 2024 }