%0 Conference Paper %1 conf/isscc/ChouLTLCCCC18 %A Chou, Chung-Cheng %A Lin, Zheng-Jun %A Tseng, Pei-Ling %A Li, Chih-Feng %A Chang, Chih-Yang %A Chen, Wei-Chi %A Chih, Yu-Der %A Chang, Tsung-Yung Jonathan %B ISSCC %D 2018 %I IEEE %K dblp %P 478-480 %T An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance. %U http://dblp.uni-trier.de/db/conf/isscc/isscc2018.html#ChouLTLCCCC18 %@ 978-1-5090-4940-0

@inproceedings{conf/isscc/ChouLTLCCCC18, added-at = {2018-03-14T00:00:00.000+0100}, author = {Chou, Chung-Cheng and Lin, Zheng-Jun and Tseng, Pei-Ling and Li, Chih-Feng and Chang, Chih-Yang and Chen, Wei-Chi and Chih, Yu-Der and Chang, Tsung-Yung Jonathan}, biburl = {https://www.bibsonomy.org/bibtex/20176f52e52aaddf93636593f4a5dd115/dblp}, booktitle = {ISSCC}, crossref = {conf/isscc/2018}, ee = {https://doi.org/10.1109/ISSCC.2018.8310392}, interhash = {350dc016b940a5eacfe927499ac57c69}, intrahash = {0176f52e52aaddf93636593f4a5dd115}, isbn = {978-1-5090-4940-0}, keywords = {dblp}, pages = {478-480}, publisher = {IEEE}, timestamp = {2018-03-15T11:37:50.000+0100}, title = {An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance.}, url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2018.html#ChouLTLCCCC18}, year = 2018 }