%0 Conference Paper %1 conf/vlsit/WangLDDLLCW22 %A Wang, Hechen %A Liu, Renzhi %A Dorrance, Richard %A Dasalukunte, Deepak %A Liu, Xiaosen %A Lake, Dan %A Carlton, Brent R. %A Wu, May %B VLSI Technology and Circuits %D 2022 %I IEEE %K dblp %P 36-37 %T A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference. %U http://dblp.uni-trier.de/db/conf/vlsit/vlsit2022.html#WangLDDLLCW22 %@ 978-1-6654-9772-5

@inproceedings{conf/vlsit/WangLDDLLCW22, added-at = {2022-10-02T00:00:00.000+0200}, author = {Wang, Hechen and Liu, Renzhi and Dorrance, Richard and Dasalukunte, Deepak and Liu, Xiaosen and Lake, Dan and Carlton, Brent R. and Wu, May}, biburl = {https://www.bibsonomy.org/bibtex/278fbd98c6f7190238ecaeb3c2e56c0f5/dblp}, booktitle = {VLSI Technology and Circuits}, crossref = {conf/vlsit/2022}, ee = {https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830322}, interhash = {3634e34511ceb7cc6969f393e3347865}, intrahash = {78fbd98c6f7190238ecaeb3c2e56c0f5}, isbn = {978-1-6654-9772-5}, keywords = {dblp}, pages = {36-37}, publisher = {IEEE}, timestamp = {2024-04-09T19:13:06.000+0200}, title = {A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference.}, url = {http://dblp.uni-trier.de/db/conf/vlsit/vlsit2022.html#WangLDDLLCW22}, year = 2022 }