%0 Conference Paper %1 conf/vlsi/VillenaS11 %A Villena, Jorge Fernandez %A Silveira, L. Miguel %B VLSI-SoC %D 2011 %I IEEE %K dblp %P 398-403 %T Positive realization of reduced RLCM nets. %U http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2011.html#VillenaS11 %@ 978-1-4577-0171-9

@inproceedings{conf/vlsi/VillenaS11, added-at = {2017-06-05T00:00:00.000+0200}, author = {Villena, Jorge Fernandez and Silveira, L. Miguel}, biburl = {https://www.bibsonomy.org/bibtex/274b220f5abc567483f2800b5bed7915f/dblp}, booktitle = {VLSI-SoC}, crossref = {conf/vlsi/2011soc}, ee = {https://doi.org/10.1109/VLSISoC.2011.6081617}, interhash = {378c8bee004de85ee2b96953186ef28c}, intrahash = {74b220f5abc567483f2800b5bed7915f}, isbn = {978-1-4577-0171-9}, keywords = {dblp}, pages = {398-403}, publisher = {IEEE}, timestamp = {2019-10-17T14:02:23.000+0200}, title = {Positive realization of reduced RLCM nets.}, url = {http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2011.html#VillenaS11}, year = 2011 }