%0 Conference Paper %1 conf/ccc/Charles91 %A Charles, Henri-Pierre %B Algorithms and Parallel VLSI Architectures %D 1991 %E Quinton, Patrice %E Robert, Yves %I Elsevier %K dblp %P 311-316 %T Loop unrolling for processors with instruction cache. %U http://dblp.uni-trier.de/db/conf/ccc/ccc1991.html#Charles91 %@ 0-444-89153-6

@inproceedings{conf/ccc/Charles91, added-at = {2002-09-04T00:00:00.000+0200}, author = {Charles, Henri-Pierre}, biburl = {https://www.bibsonomy.org/bibtex/28bc5ef8a02123fa2275bb65eb2fe713a/dblp}, booktitle = {Algorithms and Parallel VLSI Architectures}, crossref = {conf/ccc/1991}, date = {2002-09-04}, description = {dblp}, editor = {Quinton, Patrice and Robert, Yves}, interhash = {3a0ea7410b4c15646c91565ae06fccf7}, intrahash = {8bc5ef8a02123fa2275bb65eb2fe713a}, isbn = {0-444-89153-6}, keywords = {dblp}, pages = {311-316}, publisher = {Elsevier}, timestamp = {2002-09-04T00:00:00.000+0200}, title = {Loop unrolling for processors with instruction cache.}, url = {http://dblp.uni-trier.de/db/conf/ccc/ccc1991.html#Charles91}, year = 1991 }