%0 Conference Paper %1 conf/date/FavalliBM96 %A Favalli, Michele %A Benini, Luca %A Micheli, Giovanni De %B ED&TC %D 1996 %I IEEE Computer Society %K dblp %P 589-597 %T Design for Testability of Gated-Clock FSMs. %U http://dblp.uni-trier.de/db/conf/date/edtc1996.html#FavalliBM96 %@ 0-8186-7423-7

@inproceedings{conf/date/FavalliBM96, added-at = {2022-05-20T00:00:00.000+0200}, author = {Favalli, Michele and Benini, Luca and Micheli, Giovanni De}, biburl = {https://www.bibsonomy.org/bibtex/2e1e6275ec5558c15a5203da87ffeb896/dblp}, booktitle = {ED&TC}, crossref = {conf/date/1996}, ee = {https://dl.acm.org/doi/10.5555/787259.787600}, interhash = {3d88b6c9f27e4e6cfdc5a145dfa77a8b}, intrahash = {e1e6275ec5558c15a5203da87ffeb896}, isbn = {0-8186-7423-7}, keywords = {dblp}, pages = {589-597}, publisher = {IEEE Computer Society}, timestamp = {2024-04-09T12:36:13.000+0200}, title = {Design for Testability of Gated-Clock FSMs.}, url = {http://dblp.uni-trier.de/db/conf/date/edtc1996.html#FavalliBM96}, year = 1996 }