%0 Journal Article %1 journals/vlsisp/FirmansyahY22 %A Firmansyah, Iman %A Yamaguchi, Yoshiki %D 2022 %J J. Signal Process. Syst. %K dblp %N 1 %P 117-129 %T Real-Time FPGA Implementation of FIR Filter Using OpenCL Design. %U http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp94.html#FirmansyahY22 %V 94

@article{journals/vlsisp/FirmansyahY22, added-at = {2022-02-23T00:00:00.000+0100}, author = {Firmansyah, Iman and Yamaguchi, Yoshiki}, biburl = {https://www.bibsonomy.org/bibtex/2b682a8811b5e04122c3930168131f111/dblp}, ee = {https://doi.org/10.1007/s11265-021-01723-6}, interhash = {3db835d69ebc8a726e81c370b30c06fa}, intrahash = {b682a8811b5e04122c3930168131f111}, journal = {J. Signal Process. Syst.}, keywords = {dblp}, number = 1, pages = {117-129}, timestamp = {2024-04-09T03:12:22.000+0200}, title = {Real-Time FPGA Implementation of FIR Filter Using OpenCL Design.}, url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp94.html#FirmansyahY22}, volume = 94, year = 2022 }