%0 Journal Article %1 journals/jssc/JerngS05 %A Jerng, Albert C. %A Sodini, Charles G. %D 2005 %J IEEE J. Solid State Circuits %K dblp %N 2 %P 360-369 %T The impact of device type and sizing on phase noise mechanisms. %U http://dblp.uni-trier.de/db/journals/jssc/jssc40.html#JerngS05 %V 40

@article{journals/jssc/JerngS05, added-at = {2022-03-02T00:00:00.000+0100}, author = {Jerng, Albert C. and Sodini, Charles G.}, biburl = {https://www.bibsonomy.org/bibtex/2ae658bc9dce1b1bcdc59c4177b93da05/dblp}, ee = {https://doi.org/10.1109/JSSC.2004.841035}, interhash = {3f55904be11995189c696f41134b7e76}, intrahash = {ae658bc9dce1b1bcdc59c4177b93da05}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 2, pages = {360-369}, timestamp = {2024-04-08T10:42:23.000+0200}, title = {The impact of device type and sizing on phase noise mechanisms.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc40.html#JerngS05}, volume = 40, year = 2005 }