Article,

A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS.

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IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (12): 4850-4861 (2019)

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