%0 Conference Paper %1 conf/glvlsi/LiXZPHWL19 %A Li, Zhengjie %A Xiao, Yuanlong %A Zhang, Yufan %A Pang, Yunbing %A Hu, Chengyu %A Wang, Jian %A Lai, Jinmei %B ACM Great Lakes Symposium on VLSI %D 2019 %E Homayoun, Houman %E Taskin, Baris %E Mohsenin, Tinoosh %E Zhao, Weisheng %I ACM %K dblp %P 93-98 %T An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization. %U http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2019.html#LiXZPHWL19 %@ 978-1-4503-6252-8

@inproceedings{conf/glvlsi/LiXZPHWL19, added-at = {2024-02-05T00:00:00.000+0100}, author = {Li, Zhengjie and Xiao, Yuanlong and Zhang, Yufan and Pang, Yunbing and Hu, Chengyu and Wang, Jian and Lai, Jinmei}, biburl = {https://www.bibsonomy.org/bibtex/2860b5ca145e88795562694de70dec9f0/dblp}, booktitle = {ACM Great Lakes Symposium on VLSI}, crossref = {conf/glvlsi/2019}, editor = {Homayoun, Houman and Taskin, Baris and Mohsenin, Tinoosh and Zhao, Weisheng}, ee = {https://doi.org/10.1145/3299874.3318003}, interhash = {414f0880a851fee6623391483c2c849d}, intrahash = {860b5ca145e88795562694de70dec9f0}, isbn = {978-1-4503-6252-8}, keywords = {dblp}, pages = {93-98}, publisher = {ACM}, timestamp = {2024-04-09T22:51:00.000+0200}, title = {An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization.}, url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2019.html#LiXZPHWL19}, year = 2019 }