%0 Journal Article %1 journals/tvlsi/TaskinK04 %A Taskin, Baris %A Kourtev, Ivan S. %D 2004 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 1 %P 12-27 %T Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi12.html#TaskinK04 %V 12

@article{journals/tvlsi/TaskinK04, added-at = {2022-06-10T00:00:00.000+0200}, author = {Taskin, Baris and Kourtev, Ivan S.}, biburl = {https://www.bibsonomy.org/bibtex/2faa849cbdab814579c8c924ca80e8bd0/dblp}, ee = {https://doi.org/10.1109/TVLSI.2003.820525}, interhash = {4176f3d0e0050d8625ace1d1dfad60a0}, intrahash = {faa849cbdab814579c8c924ca80e8bd0}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 1, pages = {12-27}, timestamp = {2024-04-08T14:31:39.000+0200}, title = {Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi12.html#TaskinK04}, volume = 12, year = 2004 }