%0 Journal Article %1 journals/jssc/LiYZJLGZXYLX22 %A Li, Yicheng %A Yin, Yun %A Zheng, Diyang %A Jia, Xianglong %A Lin, Jie %A Gao, Fu %A Zhu, Yiting %A Xiong, Liang %A Yan, Na %A Lu, Ye %A Xu, Hongtao %D 2022 %J IEEE J. Solid State Circuits %K dblp %N 6 %P 1610-1622 %T A 15-Bit Quadrature Digital Power Amplifier With Transformer-Based Complex-Domain Efficiency Enhancement. %U http://dblp.uni-trier.de/db/journals/jssc/jssc57.html#LiYZJLGZXYLX22 %V 57

@article{journals/jssc/LiYZJLGZXYLX22, added-at = {2022-06-02T00:00:00.000+0200}, author = {Li, Yicheng and Yin, Yun and Zheng, Diyang and Jia, Xianglong and Lin, Jie and Gao, Fu and Zhu, Yiting and Xiong, Liang and Yan, Na and Lu, Ye and Xu, Hongtao}, biburl = {https://www.bibsonomy.org/bibtex/27ae230efde6ef73832f65fa9e0741826/dblp}, ee = {https://doi.org/10.1109/JSSC.2021.3128363}, interhash = {472a1e87253939d17ebf148763d7381c}, intrahash = {7ae230efde6ef73832f65fa9e0741826}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 6, pages = {1610-1622}, timestamp = {2024-04-08T10:43:29.000+0200}, title = {A 15-Bit Quadrature Digital Power Amplifier With Transformer-Based Complex-Domain Efficiency Enhancement.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc57.html#LiYZJLGZXYLX22}, volume = 57, year = 2022 }