%0 Conference Paper %1 conf/vdat/MalikKJ17 %A Malik, Munish %A Kumar, Ajay %A Jatana, H. S. %B VDAT %D 2017 %E Kaushik, Brajesh Kumar %E Dasgupta, Sudeb %E Singh, Virendra %I Springer %K dblp %P 667-678 %T Design & Development of High Speed LVDS Receiver with Cold-Spare Feature in SCL's 0.18 µm CMOS Process. %U http://dblp.uni-trier.de/db/conf/vdat/vdat2017.html#MalikKJ17 %V 711 %@ 978-981-10-7470-7

@inproceedings{conf/vdat/MalikKJ17, added-at = {2018-01-06T00:00:00.000+0100}, author = {Malik, Munish and Kumar, Ajay and Jatana, H. S.}, biburl = {https://www.bibsonomy.org/bibtex/21f327ae9b3a987974b766ccd62dbcf05/dblp}, booktitle = {VDAT}, crossref = {conf/vdat/2017}, editor = {Kaushik, Brajesh Kumar and Dasgupta, Sudeb and Singh, Virendra}, ee = {https://doi.org/10.1007/978-981-10-7470-7_63}, interhash = {486e8ceab404c6737af45f586690d171}, intrahash = {1f327ae9b3a987974b766ccd62dbcf05}, isbn = {978-981-10-7470-7}, keywords = {dblp}, pages = {667-678}, publisher = {Springer}, series = {Communications in Computer and Information Science}, timestamp = {2018-01-09T11:37:27.000+0100}, title = {Design & Development of High Speed LVDS Receiver with Cold-Spare Feature in SCL's 0.18 µm CMOS Process.}, url = {http://dblp.uni-trier.de/db/conf/vdat/vdat2017.html#MalikKJ17}, volume = 711, year = 2017 }