%0 Thesis %1 phd/ch/Afshar12 %A Parandeh-Afshar, Hadi %D 2012 %K dblp %T Closing the Gap between FPGA and ASIC - Balancing Flexibility and Efficiency.

@phdthesis{phd/ch/Afshar12, added-at = {2022-07-29T00:00:00.000+0200}, author = {Parandeh-Afshar, Hadi}, biburl = {https://www.bibsonomy.org/bibtex/2745b2de5728719bd46cffe8701be1fd2/dblp}, ee = {https://infoscience.epfl.ch/record/175046}, interhash = {4926a945c69faa97c9738cf849fe325d}, intrahash = {745b2de5728719bd46cffe8701be1fd2}, keywords = {dblp}, school = {EPFL, Switzerland}, timestamp = {2024-04-09T08:01:28.000+0200}, title = {Closing the Gap between FPGA and ASIC - Balancing Flexibility and Efficiency.}, year = 2012 }