%0 Journal Article %1 journals/tcasII/MaoWXWW24 %A Mao, Wendong %A Wang, Meiqi %A Xie, Xiaoru %A Wu, Xiao %A Wang, Zhongfeng %D 2024 %J IEEE Trans. Circuits Syst. II Express Briefs %K dblp %N 3 %P 1708-1714 %T Hardware Accelerator Design for Sparse DNN Inference and Training: A Tutorial. %U http://dblp.uni-trier.de/db/journals/tcasII/tcasII71.html#MaoWXWW24 %V 71

@article{journals/tcasII/MaoWXWW24, added-at = {2024-03-16T00:00:00.000+0100}, author = {Mao, Wendong and Wang, Meiqi and Xie, Xiaoru and Wu, Xiao and Wang, Zhongfeng}, biburl = {https://www.bibsonomy.org/bibtex/29ad9ef1860c4495efa6547d906006492/dblp}, ee = {https://doi.org/10.1109/TCSII.2023.3344681}, interhash = {498298539dfc85e82e43afe6c7c3b463}, intrahash = {9ad9ef1860c4495efa6547d906006492}, journal = {IEEE Trans. Circuits Syst. II Express Briefs}, keywords = {dblp}, month = {March}, number = 3, pages = {1708-1714}, timestamp = {2024-04-08T16:53:38.000+0200}, title = {Hardware Accelerator Design for Sparse DNN Inference and Training: A Tutorial.}, url = {http://dblp.uni-trier.de/db/journals/tcasII/tcasII71.html#MaoWXWW24}, volume = 71, year = 2024 }