%0 Journal Article %1 journals/tvlsi/YinSVETH18 %A Yin, Xunzhao %A Sedighi, Behnam %A Varga, Melinda %A Ercsey-Ravasz, Mária %A Toroczkai, Zoltán %A Hu, Xiaobo Sharon %D 2018 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 1 %P 155-167 %T Efficient Analog Circuits for Boolean Satisfiability. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi26.html#YinSVETH18 %V 26

@article{journals/tvlsi/YinSVETH18, added-at = {2020-03-11T00:00:00.000+0100}, author = {Yin, Xunzhao and Sedighi, Behnam and Varga, Melinda and Ercsey-Ravasz, Mária and Toroczkai, Zoltán and Hu, Xiaobo Sharon}, biburl = {https://www.bibsonomy.org/bibtex/2748b9df9db7766cc9e423fd29b83ddba/dblp}, ee = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2017.2754192}, interhash = {49aed0e921b2a3766970d1e1d9b2d488}, intrahash = {748b9df9db7766cc9e423fd29b83ddba}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 1, pages = {155-167}, timestamp = {2020-03-12T11:44:25.000+0100}, title = {Efficient Analog Circuits for Boolean Satisfiability.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi26.html#YinSVETH18}, volume = 26, year = 2018 }