Inproceedings,
Novel SRAM bias control circuits for a low power L1 data cache.
A. Seyedi, A. Armejach, A. Cristal, O. Unsal, and M. Valero.NORCHIP, page 1-6. IEEE, (2012)
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- conf/norchip/SeyediACUV12
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- inproceedings
- booktitle
- NORCHIP
- year
- 2012
- pages
- 1-6
- publisher
- IEEE
- crossref
- conf/norchip/2012
- ee
- https://www.wikidata.org/entity/Q61730861
- isbn
- 978-1-4673-2221-8
- url
- http://dblp.uni-trier.de/db/conf/norchip/norchip2012.html#SeyediACUV12
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%1 conf/norchip/SeyediACUV12
%A Seyedi, Azam
%A Armejach, Adrià
%A Cristal, Adrián
%A Unsal, Osman S.
%A Valero, Mateo
%B NORCHIP
%D 2012
%I IEEE
%K dblp
%P 1-6
%T Novel SRAM bias control circuits for a low power L1 data cache.
%U http://dblp.uni-trier.de/db/conf/norchip/norchip2012.html#SeyediACUV12
%@ 978-1-4673-2221-8
@inproceedings{conf/norchip/SeyediACUV12,
added-at = {2019-06-02T00:00:00.000+0200},
author = {Seyedi, Azam and Armejach, Adrià and Cristal, Adrián and Unsal, Osman S. and Valero, Mateo},
biburl = {https://www.bibsonomy.org/bibtex/2e0208ef9396ee2d8b891a614d80b0fd6/dblp},
booktitle = {NORCHIP},
crossref = {conf/norchip/2012},
ee = {https://www.wikidata.org/entity/Q61730861},
interhash = {4e34c6fa893444ec886b4c8e001318e3},
intrahash = {e0208ef9396ee2d8b891a614d80b0fd6},
isbn = {978-1-4673-2221-8},
keywords = {dblp},
pages = {1-6},
publisher = {IEEE},
timestamp = {2019-10-17T19:08:08.000+0200},
title = {Novel SRAM bias control circuits for a low power L1 data cache.},
url = {http://dblp.uni-trier.de/db/conf/norchip/norchip2012.html#SeyediACUV12},
year = 2012
}