%0 Conference Paper %1 conf/vlsid/MandrekarZCHCNDWH10 %A Mandrekar, Rohan %A Zhou, Yaping %A Chun, Sungjun %A Haridass, Anand %A Choi, Jinwoo %A Na, Nanju %A Dreps, Daniel M. %A Weekly, Roger D. %A Harvey, Paul %B VLSI Design %D 2010 %I IEEE Computer Society %K dblp %P 87-92 %T Channel Optimization for the Design of High Speed I/O links. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#MandrekarZCHCNDWH10 %@ 978-0-7695-3928-7

@inproceedings{conf/vlsid/MandrekarZCHCNDWH10, added-at = {2023-03-24T00:00:00.000+0100}, author = {Mandrekar, Rohan and Zhou, Yaping and Chun, Sungjun and Haridass, Anand and Choi, Jinwoo and Na, Nanju and Dreps, Daniel M. and Weekly, Roger D. and Harvey, Paul}, biburl = {https://www.bibsonomy.org/bibtex/258167716dc147cd63626ce50557f1088/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/2010}, ee = {https://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2010.87}, interhash = {4f3bc700711382c6b5bcf108df1f288e}, intrahash = {58167716dc147cd63626ce50557f1088}, isbn = {978-0-7695-3928-7}, keywords = {dblp}, pages = {87-92}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T04:17:37.000+0200}, title = {Channel Optimization for the Design of High Speed I/O links.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2010.html#MandrekarZCHCNDWH10}, year = 2010 }