%0 Conference Paper %1 conf/glvlsi/LinCLHCLLJ05 %A Lin, Tay-Jyi %A Chao, Chie-Min %A Liu, Chia-Hsien %A Hsiao, Pi-Chen %A Chen, Shin-Kai %A Lin, Li-Chun %A Liu, Chih-Wei %A Jen, Chein-Wei %B ACM Great Lakes Symposium on VLSI %D 2005 %E Lach, John C. %E Qu, Gang %E Ismail, Yehea I. %I ACM %K dblp %P 50-55 %T A unified processor architecture for RISC & VLIW DSP. %U http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2005.html#LinCLHCLLJ05 %@ 1-59593-057-4

@inproceedings{conf/glvlsi/LinCLHCLLJ05, added-at = {2018-11-06T00:00:00.000+0100}, author = {Lin, Tay-Jyi and Chao, Chie-Min and Liu, Chia-Hsien and Hsiao, Pi-Chen and Chen, Shin-Kai and Lin, Li-Chun and Liu, Chih-Wei and Jen, Chein-Wei}, biburl = {https://www.bibsonomy.org/bibtex/2febba0f6fbe4b18d47d341875bea8d16/dblp}, booktitle = {ACM Great Lakes Symposium on VLSI}, crossref = {conf/glvlsi/2005}, editor = {Lach, John C. and Qu, Gang and Ismail, Yehea I.}, ee = {https://doi.org/10.1145/1057661.1057675}, interhash = {5273e607006df9a969e4cbdbd6519cd3}, intrahash = {febba0f6fbe4b18d47d341875bea8d16}, isbn = {1-59593-057-4}, keywords = {dblp}, pages = {50-55}, publisher = {ACM}, timestamp = {2024-04-09T22:50:47.000+0200}, title = {A unified processor architecture for RISC & VLIW DSP.}, url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2005.html#LinCLHCLLJ05}, year = 2005 }