%0 Conference Paper %1 conf/aspdac/LiILMVPM16 %A Li, Mingzhong %A Ieong, Chio-In %A Law, Man-Kay %A Mak, Pui-In %A Vai, Mang I %A Pun, Sio-Hang %A Martins, Rui Paulo %B ASP-DAC %D 2016 %I IEEE %K dblp %P 15-16 %T Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2016.html#LiILMVPM16 %@ 978-1-4673-9569-4

@inproceedings{conf/aspdac/LiILMVPM16, added-at = {2018-11-02T00:00:00.000+0100}, author = {Li, Mingzhong and Ieong, Chio-In and Law, Man-Kay and Mak, Pui-In and Vai, Mang I and Pun, Sio-Hang and Martins, Rui Paulo}, biburl = {https://www.bibsonomy.org/bibtex/27eb6204f90711b22d53d215ab8be1a73/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2016}, ee = {https://doi.org/10.1109/ASPDAC.2016.7427979}, interhash = {53e1412e06c21699ee9b7c8e61ac957d}, intrahash = {7eb6204f90711b22d53d215ab8be1a73}, isbn = {978-1-4673-9569-4}, keywords = {dblp}, pages = {15-16}, publisher = {IEEE}, timestamp = {2019-10-17T16:46:00.000+0200}, title = {Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2016.html#LiILMVPM16}, year = 2016 }