%0 Journal Article %1 journals/vlsi/ChengS99 %A Cheng, Edward Y. C. %A Sahni, Sartaj %D 1999 %J VLSI Design %K dblp %N 2 %P 237-247 %T A Fast Algorithm for Performance-Driven Module Implementation Selection. %U http://dblp.uni-trier.de/db/journals/vlsi/vlsi10.html#ChengS99 %V 10

@article{journals/vlsi/ChengS99, added-at = {2023-05-08T00:00:00.000+0200}, author = {Cheng, Edward Y. C. and Sahni, Sartaj}, biburl = {https://www.bibsonomy.org/bibtex/27c01827e3d56dfaa9aa4fb772b1d2e4c/dblp}, ee = {https://doi.org/10.1155/1999/67373}, interhash = {557bfe63981065592abf19ed2c0a16b6}, intrahash = {7c01827e3d56dfaa9aa4fb772b1d2e4c}, journal = {VLSI Design}, keywords = {dblp}, number = 2, pages = {237-247}, timestamp = {2024-04-08T12:07:43.000+0200}, title = {A Fast Algorithm for Performance-Driven Module Implementation Selection.}, url = {http://dblp.uni-trier.de/db/journals/vlsi/vlsi10.html#ChengS99}, volume = 10, year = 1999 }