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%0 Journal Article
%1 journals/tcasII/ZhangTLWWZZZZ24
%A Zhang, Kaili
%A Tong, Zhongzhen
%A Liang, Xinxin
%A Wang, Chengzhi
%A Wang, You
%A Zhang, Yue
%A Zhao, Weisheng
%A Zeng, Lang
%A Zhang, Deming
%D 2024
%J IEEE Trans. Circuits Syst. II Express Briefs
%K dblp
%N 3
%P 1077-1081
%T A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation.
%U http://dblp.uni-trier.de/db/journals/tcasII/tcasII71.html#ZhangTLWWZZZZ24
%V 71
@article{journals/tcasII/ZhangTLWWZZZZ24,
added-at = {2024-03-16T00:00:00.000+0100},
author = {Zhang, Kaili and Tong, Zhongzhen and Liang, Xinxin and Wang, Chengzhi and Wang, You and Zhang, Yue and Zhao, Weisheng and Zeng, Lang and Zhang, Deming},
biburl = {https://www.bibsonomy.org/bibtex/2790da1af918095dd3a3f3bdab83e08d8/dblp},
ee = {https://doi.org/10.1109/TCSII.2023.3322556},
interhash = {57316ef02290f3cd04866ff8caaf636a},
intrahash = {790da1af918095dd3a3f3bdab83e08d8},
journal = {IEEE Trans. Circuits Syst. II Express Briefs},
keywords = {dblp},
month = {March},
number = 3,
pages = {1077-1081},
timestamp = {2024-04-08T16:53:47.000+0200},
title = {A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation.},
url = {http://dblp.uni-trier.de/db/journals/tcasII/tcasII71.html#ZhangTLWWZZZZ24},
volume = 71,
year = 2024
}
