%0 Conference Paper %1 conf/iscas/HsuSYJLW09 %A Hsu, Chia-Hao %A Sung, Gang-Neng %A Yao, Tuo-Yu %A Juan, Chun-Ying %A Lin, Yain-Reu %A Wang, Chua-Chin %B ISCAS %D 2009 %I IEEE %K dblp %P 389-392 %T Low-power 7.2 GHz Complementary All-N-Transistor Logic using 90 nm CMOS Technology. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2009.html#HsuSYJLW09 %@ 978-1-4244-3828-0

@inproceedings{conf/iscas/HsuSYJLW09, added-at = {2011-06-28T00:00:00.000+0200}, author = {Hsu, Chia-Hao and Sung, Gang-Neng and Yao, Tuo-Yu and Juan, Chun-Ying and Lin, Yain-Reu and Wang, Chua-Chin}, biburl = {https://www.bibsonomy.org/bibtex/21f7c5b57fa93ed577590399b4286c33e/dblp}, booktitle = {ISCAS}, crossref = {conf/iscas/2009}, ee = {http://dx.doi.org/10.1109/ISCAS.2009.5117767}, interhash = {5782d1f8fefdb0c158be530a5800f5bb}, intrahash = {1f7c5b57fa93ed577590399b4286c33e}, isbn = {978-1-4244-3828-0}, keywords = {dblp}, pages = {389-392}, publisher = {IEEE}, timestamp = {2016-05-21T11:41:44.000+0200}, title = {Low-power 7.2 GHz Complementary All-N-Transistor Logic using 90 nm CMOS Technology.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2009.html#HsuSYJLW09}, year = 2009 }