%0 Journal Article %1 journals/jssc/JiaoGK10 %A Jiao, Dong %A Gu, Jie %A Kim, Chris H. %D 2010 %J IEEE J. Solid State Circuits %K dblp %N 10 %P 2130-2141 %T Circuit Design and Modeling Techniques for Enhancing the Clock-Data Compensation Effect Under Resonant Supply Noise. %U http://dblp.uni-trier.de/db/journals/jssc/jssc45.html#JiaoGK10 %V 45

@article{journals/jssc/JiaoGK10, added-at = {2021-03-02T00:00:00.000+0100}, author = {Jiao, Dong and Gu, Jie and Kim, Chris H.}, biburl = {https://www.bibsonomy.org/bibtex/293351a7126e5c239a1d5de66dc5d79ae/dblp}, ee = {https://doi.org/10.1109/JSSC.2010.2063931}, interhash = {58a56c01ee9ca92faba67d10a87eb0f2}, intrahash = {93351a7126e5c239a1d5de66dc5d79ae}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 10, pages = {2130-2141}, timestamp = {2024-04-08T10:43:37.000+0200}, title = {Circuit Design and Modeling Techniques for Enhancing the Clock-Data Compensation Effect Under Resonant Supply Noise.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc45.html#JiaoGK10}, volume = 45, year = 2010 }