%0 Journal Article %1 journals/ieicet/WangBDM07 %A min Wang, Wei %A yan Bi, Du %A Du, Xingmin %A hua Ma, Lin %D 2007 %J IEICE Trans. Inf. Syst. %K dblp %N 8 %P 1301-1303 %T A VLSI Design of a Pipelining and Area-Efficient Reed-Solomon Decoder. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet90d.html#WangBDM07 %V 90-D

@article{journals/ieicet/WangBDM07, added-at = {2020-04-11T00:00:00.000+0200}, author = {min Wang, Wei and yan Bi, Du and Du, Xingmin and hua Ma, Lin}, biburl = {https://www.bibsonomy.org/bibtex/2122a1feb6e7fd9cddc346dda665d0c25/dblp}, ee = {https://doi.org/10.1093/ietisy/e90-d.8.1301}, interhash = {59ed2406db8f841408246737311f1271}, intrahash = {122a1feb6e7fd9cddc346dda665d0c25}, journal = {IEICE Trans. Inf. Syst.}, keywords = {dblp}, number = 8, pages = {1301-1303}, timestamp = {2020-04-14T11:54:56.000+0200}, title = {A VLSI Design of a Pipelining and Area-Efficient Reed-Solomon Decoder.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet90d.html#WangBDM07}, volume = {90-D}, year = 2007 }