%0 Journal Article %1 journals/vlsisp/HuaiZZ22 %A Huai, Zheang %A Zhou, Jingbo %A Zhang, Xinmiao %D 2022 %J J. Signal Process. Syst. %K dblp %N 10 %P 1067-1082 %T Efficient Hardware Implementation Architectures for Long Integer Modular Multiplication over General Solinas Prime. %U http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp94.html#HuaiZZ22 %V 94

@article{journals/vlsisp/HuaiZZ22, added-at = {2023-08-28T00:00:00.000+0200}, author = {Huai, Zheang and Zhou, Jingbo and Zhang, Xinmiao}, biburl = {https://www.bibsonomy.org/bibtex/2f569567a8e0be5b85587a2c4f7a29933/dblp}, ee = {https://www.wikidata.org/entity/Q113900384}, interhash = {5aa02267b0541cb9ea6158f4e5934d72}, intrahash = {f569567a8e0be5b85587a2c4f7a29933}, journal = {J. Signal Process. Syst.}, keywords = {dblp}, number = 10, pages = {1067-1082}, timestamp = {2024-04-09T03:12:37.000+0200}, title = {Efficient Hardware Implementation Architectures for Long Integer Modular Multiplication over General Solinas Prime.}, url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp94.html#HuaiZZ22}, volume = 94, year = 2022 }