%0 Conference Paper %1 conf/vlsi-dat/ChenHL15 %A Chen, Yu-Chuan %A Hsu, Chih-Cheng %A Lin, Mark Po-Hung %B VLSI-DAT %D 2015 %I IEEE %K dblp %P 1-4 %T Low-power gated clock tree optimization for three-dimensional integrated circuits. %U http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2015.html#ChenHL15 %@ 978-1-4799-6275-4

@inproceedings{conf/vlsi-dat/ChenHL15, added-at = {2023-11-12T00:00:00.000+0100}, author = {Chen, Yu-Chuan and Hsu, Chih-Cheng and Lin, Mark Po-Hung}, biburl = {https://www.bibsonomy.org/bibtex/28ef4fe90a1db0203e35407af79018dba/dblp}, booktitle = {VLSI-DAT}, crossref = {conf/vlsi-dat/2015}, ee = {https://doi.org/10.1109/VLSI-DAT.2015.7114530}, interhash = {5b7adf3a43a8482ea95a8c3db9ae3fef}, intrahash = {8ef4fe90a1db0203e35407af79018dba}, isbn = {978-1-4799-6275-4}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2024-04-10T19:50:05.000+0200}, title = {Low-power gated clock tree optimization for three-dimensional integrated circuits.}, url = {http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2015.html#ChenHL15}, year = 2015 }