%0 Conference Paper %1 conf/dac/WeiYZCWHLC17 %A Wei, Xuechao %A Yu, Cody Hao %A Zhang, Peng %A Chen, Youxiang %A Wang, Yuxin %A Hu, Han %A Liang, Yun %A Cong, Jason %B DAC %D 2017 %I ACM %K dblp %P 29:1-29:6 %T Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs. %U http://dblp.uni-trier.de/db/conf/dac/dac2017.html#WeiYZCWHLC17 %@ 978-1-4503-4927-7

@inproceedings{conf/dac/WeiYZCWHLC17, added-at = {2020-09-30T00:00:00.000+0200}, author = {Wei, Xuechao and Yu, Cody Hao and Zhang, Peng and Chen, Youxiang and Wang, Yuxin and Hu, Han and Liang, Yun and Cong, Jason}, biburl = {https://www.bibsonomy.org/bibtex/2f321392b54d603e2a4ee6b30c57b1dfe/dblp}, booktitle = {DAC}, crossref = {conf/dac/2017}, ee = {https://doi.org/10.1145/3061639.3062207}, interhash = {5ba6be1d7e41ad87162baeaea324fa4d}, intrahash = {f321392b54d603e2a4ee6b30c57b1dfe}, isbn = {978-1-4503-4927-7}, keywords = {dblp}, pages = {29:1-29:6}, publisher = {ACM}, timestamp = {2020-10-01T11:40:08.000+0200}, title = {Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs.}, url = {http://dblp.uni-trier.de/db/conf/dac/dac2017.html#WeiYZCWHLC17}, year = 2017 }