%0 Journal Article %1 journals/tsp/ChenHCCC06 %A Chen, Ching-Yeh %A Huang, Chao-Tsung %A Chen, Yi-Hau %A Chien, Shao-Yi %A Chen, Liang-Gee %D 2006 %J IEEE Trans. Signal Process. %K dblp %N 10 %P 4004-4014 %T System Analysis of VLSI Architecture for 5/3 and 1/3 Motion-Compensated Temporal Filtering. %U http://dblp.uni-trier.de/db/journals/tsp/tsp54.html#ChenHCCC06 %V 54

@article{journals/tsp/ChenHCCC06, added-at = {2020-06-16T00:00:00.000+0200}, author = {Chen, Ching-Yeh and Huang, Chao-Tsung and Chen, Yi-Hau and Chien, Shao-Yi and Chen, Liang-Gee}, biburl = {https://www.bibsonomy.org/bibtex/2dc97c01e2726afbb069b081baf7982ef/dblp}, ee = {https://doi.org/10.1109/TSP.2006.880202}, interhash = {5cd6f3f9acc6f1d41da1a43e1cc67ee8}, intrahash = {dc97c01e2726afbb069b081baf7982ef}, journal = {IEEE Trans. Signal Process.}, keywords = {dblp}, number = 10, pages = {4004-4014}, timestamp = {2020-06-17T11:48:27.000+0200}, title = {System Analysis of VLSI Architecture for 5/3 and 1/3 Motion-Compensated Temporal Filtering.}, url = {http://dblp.uni-trier.de/db/journals/tsp/tsp54.html#ChenHCCC06}, volume = 54, year = 2006 }