%0 Conference Paper %1 conf/iastedCCS/LinYZSX05 %A Lin, Zengjin %A Yang, Haigang %A Zhong, Lungui %A Sun, Jiabin %A Xia, Shanhong %B Circuits, Signals, and Systems %D 2005 %E Oklobdzija, Vojin G. %I IASTED/ACTA Press %K dblp %P 165-168 %T Impact of capacitor array mismatch in embedded CMOS CR SAR ADC design. %U http://dblp.uni-trier.de/db/conf/iastedCCS/iastedCCS2005.html#LinYZSX05 %@ 0-88986-509-4

@inproceedings{conf/iastedCCS/LinYZSX05, added-at = {2007-01-25T00:00:00.000+0100}, author = {Lin, Zengjin and Yang, Haigang and Zhong, Lungui and Sun, Jiabin and Xia, Shanhong}, biburl = {https://www.bibsonomy.org/bibtex/2de0cbccb26f2d45d2838bac2976af747/dblp}, booktitle = {Circuits, Signals, and Systems}, crossref = {conf/iastedCCS/2005}, date = {2007-01-25}, description = {dblp}, editor = {Oklobdzija, Vojin G.}, interhash = {6187faaa7ea94064b495e546678ce6e2}, intrahash = {de0cbccb26f2d45d2838bac2976af747}, isbn = {0-88986-509-4}, keywords = {dblp}, pages = {165-168}, publisher = {IASTED/ACTA Press}, timestamp = {2007-02-07T11:16:45.000+0100}, title = {Impact of capacitor array mismatch in embedded CMOS CR SAR ADC design.}, url = {http://dblp.uni-trier.de/db/conf/iastedCCS/iastedCCS2005.html#LinYZSX05}, year = 2005 }