%0 Conference Paper %1 conf/globecom/ChenH03 %A Chen, Yanni %A Hocevar, Dale E. %B GLOBECOM %D 2003 %I IEEE %K dblp %P 113-117 %T A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder. %U http://dblp.uni-trier.de/db/conf/globecom/globecom2003.html#ChenH03 %@ 0-7803-7974-8

@inproceedings{conf/globecom/ChenH03, added-at = {2017-05-23T00:00:00.000+0200}, author = {Chen, Yanni and Hocevar, Dale E.}, biburl = {https://www.bibsonomy.org/bibtex/2d57c9e091193318010500941c7e9c850/dblp}, booktitle = {GLOBECOM}, crossref = {conf/globecom/2003}, ee = {https://doi.org/10.1109/GLOCOM.2003.1258213}, interhash = {64e53bd8e7aa3fc923292e67c145b940}, intrahash = {d57c9e091193318010500941c7e9c850}, isbn = {0-7803-7974-8}, keywords = {dblp}, pages = {113-117}, publisher = {IEEE}, timestamp = {2019-10-17T19:41:52.000+0200}, title = {A FPGA and ASIC implementation of rate 1/2, 8088-b irregular low density parity check decoder.}, url = {http://dblp.uni-trier.de/db/conf/globecom/globecom2003.html#ChenH03}, year = 2003 }