%0 Journal Article %1 journals/vlsisp/SunnyDMC22 %A Sunny, Chilankamol %A Das, Satyajit %A Martin, Kevin J. M. %A Coussy, Philippe %D 2022 %J J. Signal Process. Syst. %K dblp %N 9 %P 895-912 %T Energy Efficient Hardware Loop Based Optimization for CGRAs. %U http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp94.html#SunnyDMC22 %V 94

@article{journals/vlsisp/SunnyDMC22, added-at = {2023-08-28T00:00:00.000+0200}, author = {Sunny, Chilankamol and Das, Satyajit and Martin, Kevin J. M. and Coussy, Philippe}, biburl = {https://www.bibsonomy.org/bibtex/23a98e9e58d6aa3a3e90c2724b79b8eed/dblp}, ee = {https://www.wikidata.org/entity/Q113900388}, interhash = {6519a3d1b1fd9d959cb3e7e0ca5ae2c6}, intrahash = {3a98e9e58d6aa3a3e90c2724b79b8eed}, journal = {J. Signal Process. Syst.}, keywords = {dblp}, number = 9, pages = {895-912}, timestamp = {2024-04-09T03:12:16.000+0200}, title = {Energy Efficient Hardware Loop Based Optimization for CGRAs.}, url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp94.html#SunnyDMC22}, volume = 94, year = 2022 }