%0 Journal Article %1 journals/tcad/SubramanyanHVGM18 %A Subramanyan, Pramod %A Huang, Bo-Yuan %A Vizel, Yakir %A Gupta, Aarti %A Malik, Sharad %D 2018 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 8 %P 1692-1705 %T Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification. %U http://dblp.uni-trier.de/db/journals/tcad/tcad37.html#SubramanyanHVGM18 %V 37

@article{journals/tcad/SubramanyanHVGM18, added-at = {2023-09-30T00:00:00.000+0200}, author = {Subramanyan, Pramod and Huang, Bo-Yuan and Vizel, Yakir and Gupta, Aarti and Malik, Sharad}, biburl = {https://www.bibsonomy.org/bibtex/2ba3acff794893f26371df0a00db26109/dblp}, ee = {https://doi.org/10.1109/TCAD.2017.2764482}, interhash = {67e315c0926d9ac8a7baa38266b2a085}, intrahash = {ba3acff794893f26371df0a00db26109}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 8, pages = {1692-1705}, timestamp = {2024-04-08T19:46:20.000+0200}, title = {Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad37.html#SubramanyanHVGM18}, volume = 37, year = 2018 }