Inproceedings,
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters.
P. Vivet, E. Guthmuller, Y. Thonnart, G. Pillonnet, G. Moritz, I. Miro-Panades, C. Tortolero, J. Durupt, C. Bernard, D. Varreau, J. Pontes, S. Thuries, D. Coriat, M. Harrand, D. Dutoit, D. Lattard, L. Arnaud, J. Charbonnier, P. Coudrain, A. Garnier, F. Berger, A. Gueugnot, A. Greiner, Q. Meunier, A. Farcy, A. Arriordaz, S. Cheramy, and F. Clermidy.ISSCC, page 46-48. IEEE, (2020)
Meta data
- BibTeX key
- conf/isscc/VivetGTPMMTDBVP20
- entry type
- inproceedings
- booktitle
- ISSCC
- year
- 2020
- pages
- 46-48
- publisher
- IEEE
- crossref
- conf/isscc/2020
- ee
- https://doi.org/10.1109/ISSCC19947.2020.9062927
- isbn
- 978-1-7281-3205-1
- url
- http://dblp.uni-trier.de/db/conf/isscc/isscc2020.html#VivetGTPMMTDBVP20
Tags
Users
Comments and Reviewsshow / hide
Cite this publication
More citation styles
- please select -%0 Conference Paper
%1 conf/isscc/VivetGTPMMTDBVP20
%A Vivet, Pascal
%A Guthmuller, Eric
%A Thonnart, Yvain
%A Pillonnet, Gaël
%A Moritz, Guillaume
%A Miro-Panades, Ivan
%A Tortolero, César Fuguet
%A Durupt, Jean
%A Bernard, Christian
%A Varreau, Didier
%A Pontes, Julian J. H.
%A Thuries, Sébastien
%A Coriat, David
%A Harrand, Michel
%A Dutoit, Denis
%A Lattard, Didier
%A Arnaud, Lucile
%A Charbonnier, Jean
%A Coudrain, Perceval
%A Garnier, Arnaud
%A Berger, Frédéric
%A Gueugnot, Alain
%A Greiner, Alain
%A Meunier, Quentin L.
%A Farcy, Alexis
%A Arriordaz, Alexandre
%A Cheramy, Séverine
%A Clermidy, Fabien
%B ISSCC
%D 2020
%I IEEE
%K dblp
%P 46-48
%T 2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters.
%U http://dblp.uni-trier.de/db/conf/isscc/isscc2020.html#VivetGTPMMTDBVP20
%@ 978-1-7281-3205-1
@inproceedings{conf/isscc/VivetGTPMMTDBVP20,
added-at = {2024-05-07T00:00:00.000+0200},
author = {Vivet, Pascal and Guthmuller, Eric and Thonnart, Yvain and Pillonnet, Gaël and Moritz, Guillaume and Miro-Panades, Ivan and Tortolero, César Fuguet and Durupt, Jean and Bernard, Christian and Varreau, Didier and Pontes, Julian J. H. and Thuries, Sébastien and Coriat, David and Harrand, Michel and Dutoit, Denis and Lattard, Didier and Arnaud, Lucile and Charbonnier, Jean and Coudrain, Perceval and Garnier, Arnaud and Berger, Frédéric and Gueugnot, Alain and Greiner, Alain and Meunier, Quentin L. and Farcy, Alexis and Arriordaz, Alexandre and Cheramy, Séverine and Clermidy, Fabien},
biburl = {https://www.bibsonomy.org/bibtex/28f03931446ae389fd44e36a04fd6a56e/dblp},
booktitle = {ISSCC},
crossref = {conf/isscc/2020},
ee = {https://doi.org/10.1109/ISSCC19947.2020.9062927},
interhash = {69460651264aebf56c776f77b346ebe1},
intrahash = {8f03931446ae389fd44e36a04fd6a56e},
isbn = {978-1-7281-3205-1},
keywords = {dblp},
pages = {46-48},
publisher = {IEEE},
timestamp = {2024-05-13T09:02:23.000+0200},
title = {2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters.},
url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2020.html#VivetGTPMMTDBVP20},
year = 2020
}