%0 Conference Paper %1 conf/glvlsi/YangMW19 %A Yang, Zongxian %A Ma, Yixiao %A Wei, Lan %B ACM Great Lakes Symposium on VLSI %D 2019 %E Homayoun, Houman %E Taskin, Baris %E Mohsenin, Tinoosh %E Zhao, Weisheng %I ACM %K dblp %P 147-152 %T Functionally Complete Boolean Logic and Adder Design Based on 2T2R RRAMs for Post-CMOS In-Memory Computing. %U http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2019.html#YangMW19 %@ 978-1-4503-6252-8

@inproceedings{conf/glvlsi/YangMW19, added-at = {2019-05-16T00:00:00.000+0200}, author = {Yang, Zongxian and Ma, Yixiao and Wei, Lan}, biburl = {https://www.bibsonomy.org/bibtex/2b4446bf316edaf8020a3a5210b818396/dblp}, booktitle = {ACM Great Lakes Symposium on VLSI}, crossref = {conf/glvlsi/2019}, editor = {Homayoun, Houman and Taskin, Baris and Mohsenin, Tinoosh and Zhao, Weisheng}, ee = {https://doi.org/10.1145/3299874.3317993}, interhash = {6a8c408c75fa693d2a2343c7027711b4}, intrahash = {b4446bf316edaf8020a3a5210b818396}, isbn = {978-1-4503-6252-8}, keywords = {dblp}, pages = {147-152}, publisher = {ACM}, timestamp = {2024-04-09T22:51:00.000+0200}, title = {Functionally Complete Boolean Logic and Adder Design Based on 2T2R RRAMs for Post-CMOS In-Memory Computing.}, url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi2019.html#YangMW19}, year = 2019 }