%0 Journal Article %1 journals/iet-cds/GoelSG12 %A Goel, Ankur %A Sharma, Rohit K. %A Gupta, A. K. %D 2012 %J IET Circuits Devices Syst. %K dblp %N 1 %P 45-51 %T Process variations aware area efficient negative bit-line voltage scheme for improving write ability of SRAM in nanometer technologies. %U http://dblp.uni-trier.de/db/journals/iet-cds/iet-cds6.html#GoelSG12 %V 6

@article{journals/iet-cds/GoelSG12, added-at = {2020-09-10T00:00:00.000+0200}, author = {Goel, Ankur and Sharma, Rohit K. and Gupta, A. K.}, biburl = {https://www.bibsonomy.org/bibtex/29a8476789f6c69f0510057c0c20d43b9/dblp}, ee = {https://doi.org/10.1049/iet-cds.2011.0036}, interhash = {6bf8aac8d979387a1a4ed50c71e95293}, intrahash = {9a8476789f6c69f0510057c0c20d43b9}, journal = {IET Circuits Devices Syst.}, keywords = {dblp}, number = 1, pages = {45-51}, timestamp = {2020-09-11T11:44:44.000+0200}, title = {Process variations aware area efficient negative bit-line voltage scheme for improving write ability of SRAM in nanometer technologies.}, url = {http://dblp.uni-trier.de/db/journals/iet-cds/iet-cds6.html#GoelSG12}, volume = 6, year = 2012 }