%0 Conference Paper %1 conf/vlsid/ParekhjiVS93 %A Parekhji, Rubin A. %A Venkatesh, G. %A Sherlekar, Sunil D. %B VLSI Design %D 1993 %I IEEE Computer Society %K dblp %P 15-20 %T State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid1993.html#ParekhjiVS93 %@ 0-8186-3180-5

@inproceedings{conf/vlsid/ParekhjiVS93, added-at = {2023-03-24T00:00:00.000+0100}, author = {Parekhji, Rubin A. and Venkatesh, G. and Sherlekar, Sunil D.}, biburl = {https://www.bibsonomy.org/bibtex/20ccb31871efdc7f8a1c818f95a3b06be/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/1993}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.1993.669627}, interhash = {6ef0839c04d843ad9f7a8266ba44e590}, intrahash = {0ccb31871efdc7f8a1c818f95a3b06be}, isbn = {0-8186-3180-5}, keywords = {dblp}, pages = {15-20}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T05:46:57.000+0200}, title = {State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid1993.html#ParekhjiVS93}, year = 1993 }