%0 Conference Paper %1 conf/vlsid/BandyopadhyayJJ97 %A Bandyopadhyay, Subir %A Jaekel, Arunita %A Jullien, Graham A. %B VLSI Design %D 1997 %I IEEE Computer Society %K dblp %P 516-519 %T A Method for Synthesizing Area Efficient Multilevel PTL Circuits. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid1997.html#BandyopadhyayJJ97 %@ 0-8186-7755-4

@inproceedings{conf/vlsid/BandyopadhyayJJ97, added-at = {2023-03-24T00:00:00.000+0100}, author = {Bandyopadhyay, Subir and Jaekel, Arunita and Jullien, Graham A.}, biburl = {https://www.bibsonomy.org/bibtex/29196fed40829bbb33292ba9a34e40f8c/dblp}, booktitle = {VLSI Design}, crossref = {conf/vlsid/1997}, ee = {https://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568191}, interhash = {73089756e4806607549953695b483a64}, intrahash = {9196fed40829bbb33292ba9a34e40f8c}, isbn = {0-8186-7755-4}, keywords = {dblp}, pages = {516-519}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T05:47:27.000+0200}, title = {A Method for Synthesizing Area Efficient Multilevel PTL Circuits.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid1997.html#BandyopadhyayJJ97}, year = 1997 }