%0 Journal Article %1 journals/tcasI/AbdAlRahmanSSR24 %A AbdAlRahman, Alaa %A Said, Lobna A. %A Soltan, Ahmed %A Radwan, Ahmed G. %D 2024 %J IEEE Trans. Circuits Syst. I Regul. Pap. %K dblp %N 2 %P 680-688 %T Hardware Accelerator of Fractional-Order Operator Based on Phase Optimized Filters With Applications. %U http://dblp.uni-trier.de/db/journals/tcasI/tcasI71.html#AbdAlRahmanSSR24 %V 71

@article{journals/tcasI/AbdAlRahmanSSR24, added-at = {2024-02-29T00:00:00.000+0100}, author = {AbdAlRahman, Alaa and Said, Lobna A. and Soltan, Ahmed and Radwan, Ahmed G.}, biburl = {https://www.bibsonomy.org/bibtex/235ed175335c980b82e2cc910e5879703/dblp}, ee = {https://doi.org/10.1109/TCSI.2023.3342695}, interhash = {743f014af6163a72e794e792101cca3b}, intrahash = {35ed175335c980b82e2cc910e5879703}, journal = {IEEE Trans. Circuits Syst. I Regul. Pap.}, keywords = {dblp}, month = {February}, number = 2, pages = {680-688}, timestamp = {2024-04-08T16:47:48.000+0200}, title = {Hardware Accelerator of Fractional-Order Operator Based on Phase Optimized Filters With Applications.}, url = {http://dblp.uni-trier.de/db/journals/tcasI/tcasI71.html#AbdAlRahmanSSR24}, volume = 71, year = 2024 }