%0 Conference Paper %1 conf/vlsic/LuSCRHCCCC21 %A Lu, Nicky %A Shiah, Chun %A Chueh, Juang-Ying %A Rong, Bor-Doou %A Huang, Wei-Jr %A Chen, Ho-Yin %A Chang, Cheng-Nan %A Chang, Chia-Wei %A Chen, Tzung-Shen %B VLSI Circuits %D 2021 %I IEEE %K dblp %P 1-2 %T Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns. %U http://dblp.uni-trier.de/db/conf/vlsic/vlsic2021.html#LuSCRHCCCC21 %@ 978-4-86348-780-2

@inproceedings{conf/vlsic/LuSCRHCCCC21, added-at = {2021-08-02T00:00:00.000+0200}, author = {Lu, Nicky and Shiah, Chun and Chueh, Juang-Ying and Rong, Bor-Doou and Huang, Wei-Jr and Chen, Ho-Yin and Chang, Cheng-Nan and Chang, Chia-Wei and Chen, Tzung-Shen}, biburl = {https://www.bibsonomy.org/bibtex/23e7ca2ccaecfadd9ecdd14953f6c3944/dblp}, booktitle = {VLSI Circuits}, crossref = {conf/vlsic/2021}, ee = {https://doi.org/10.23919/VLSICircuits52068.2021.9492418}, interhash = {77ef5ba8ad2e5452b91bde7b21fb0d05}, intrahash = {3e7ca2ccaecfadd9ecdd14953f6c3944}, isbn = {978-4-86348-780-2}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2024-04-09T21:13:43.000+0200}, title = {Enhanced Core Circuits for scaling DRAM: 0.7V VCC with Long Retention 138ms at 125°C and Random Row/Column Access Times Accelerated by 1.5ns.}, url = {http://dblp.uni-trier.de/db/conf/vlsic/vlsic2021.html#LuSCRHCCCC21}, year = 2021 }