%0 Journal Article %1 journals/jssc/KaenelAPD96 %A von Kaenel, Vincent %A Aebischer, Daniel %A Piguet, Christian %A Dijkstra, Evert %D 1996 %J IEEE J. Solid State Circuits %K dblp %N 11 %P 1715-1722 %T A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation. %U http://dblp.uni-trier.de/db/journals/jssc/jssc31.html#KaenelAPD96 %V 31

@article{journals/jssc/KaenelAPD96, added-at = {2022-07-18T00:00:00.000+0200}, author = {von Kaenel, Vincent and Aebischer, Daniel and Piguet, Christian and Dijkstra, Evert}, biburl = {https://www.bibsonomy.org/bibtex/27eb2d6e0e67768f9aca4f6ad7fd6878a/dblp}, ee = {https://doi.org/10.1109/JSSC.1996.542316}, interhash = {7949d3c445a4c05e376846c6eaf7a7f2}, intrahash = {7eb2d6e0e67768f9aca4f6ad7fd6878a}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 11, pages = {1715-1722}, timestamp = {2024-04-08T10:44:35.000+0200}, title = {A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc31.html#KaenelAPD96}, volume = 31, year = 1996 }