%0 Journal Article %1 journals/jsa/EshraghianSCN91 %A Eshraghian, K. %A Sarmiento, Roberto %A Carballo, Pedro P. %A Núñez, Antonio %D 1991 %J Microprocessing and Microprogramming %K dblp %N 1-5 %P 75-82 %T Speed-area-power optimization for DCFL and SDCFL class of logic using ring notation. %U http://dblp.uni-trier.de/db/journals/jsa/jsa32.html#EshraghianSCN91 %V 32

@article{journals/jsa/EshraghianSCN91, added-at = {2022-10-20T00:00:00.000+0200}, author = {Eshraghian, K. and Sarmiento, Roberto and Carballo, Pedro P. and Núñez, Antonio}, biburl = {https://www.bibsonomy.org/bibtex/26095555d35fa85769f988327159b4b97/dblp}, ee = {https://doi.org/10.1016/0165-6074(91)90326-O}, interhash = {7b751447c805aa8ffd8dcd19c0751394}, intrahash = {6095555d35fa85769f988327159b4b97}, journal = {Microprocessing and Microprogramming}, keywords = {dblp}, number = {1-5}, pages = {75-82}, timestamp = {2024-04-09T07:10:39.000+0200}, title = {Speed-area-power optimization for DCFL and SDCFL class of logic using ring notation.}, url = {http://dblp.uni-trier.de/db/journals/jsa/jsa32.html#EshraghianSCN91}, volume = 32, year = 1991 }