%0 Conference Paper %1 conf/fpt/TanigawaH08 %A Tanigawa, Kazuya %A Hironaka, Tetsuo %B FPT %D 2008 %E El-Ghazawi, Tarek A. %E Chang, Yao-Wen %E Huang, Juinn-Dar %E Saha, Proshanta %I IEEE %K dblp %P 273-276 %T Evaluation of compact high-throughput reconfigurable architecture based on bit-serial computation. %U http://dblp.uni-trier.de/db/conf/fpt/fpt2008.html#TanigawaH08 %@ 978-1-4244-2796-3

@inproceedings{conf/fpt/TanigawaH08, added-at = {2017-05-24T00:00:00.000+0200}, author = {Tanigawa, Kazuya and Hironaka, Tetsuo}, biburl = {https://www.bibsonomy.org/bibtex/202a1c227cd24e47ae0169bf6962b7d1e/dblp}, booktitle = {FPT}, crossref = {conf/fpt/2008}, editor = {El-Ghazawi, Tarek A. and Chang, Yao-Wen and Huang, Juinn-Dar and Saha, Proshanta}, ee = {https://doi.org/10.1109/FPT.2008.4762396}, interhash = {7c8b1d63f89f129fd9d5e9464b11f5cd}, intrahash = {02a1c227cd24e47ae0169bf6962b7d1e}, isbn = {978-1-4244-2796-3}, keywords = {dblp}, pages = {273-276}, publisher = {IEEE}, timestamp = {2019-10-17T23:10:06.000+0200}, title = {Evaluation of compact high-throughput reconfigurable architecture based on bit-serial computation.}, url = {http://dblp.uni-trier.de/db/conf/fpt/fpt2008.html#TanigawaH08}, year = 2008 }