%0 Conference Paper %1 conf/vdat/MaheshwaramPSBM17 %A Maheshwaram, Satish %A Prakash, Om. %A Sharma, Mohit %A Bulusu, Anand %A Manhas, Sanjeev %B VDAT %D 2017 %E Kaushik, Brajesh Kumar %E Dasgupta, Sudeb %E Singh, Virendra %I Springer %K dblp %P 239-248 %T Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance. %U http://dblp.uni-trier.de/db/conf/vdat/vdat2017.html#MaheshwaramPSBM17 %V 711 %@ 978-981-10-7470-7

@inproceedings{conf/vdat/MaheshwaramPSBM17, added-at = {2023-08-17T00:00:00.000+0200}, author = {Maheshwaram, Satish and Prakash, Om. and Sharma, Mohit and Bulusu, Anand and Manhas, Sanjeev}, biburl = {https://www.bibsonomy.org/bibtex/2f94b6611f197283c53545e7c34c54f26/dblp}, booktitle = {VDAT}, crossref = {conf/vdat/2017}, editor = {Kaushik, Brajesh Kumar and Dasgupta, Sudeb and Singh, Virendra}, ee = {https://doi.org/10.1007/978-981-10-7470-7_24}, interhash = {7cf4149d2b5427843c74995aa15ab39b}, intrahash = {f94b6611f197283c53545e7c34c54f26}, isbn = {978-981-10-7470-7}, keywords = {dblp}, pages = {239-248}, publisher = {Springer}, series = {Communications in Computer and Information Science}, timestamp = {2024-04-10T13:46:15.000+0200}, title = {Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance.}, url = {http://dblp.uni-trier.de/db/conf/vdat/vdat2017.html#MaheshwaramPSBM17}, volume = 711, year = 2017 }