%0 Conference Paper %1 conf/aspdac/HuangCC97 %A Huang, Shi-Yu %A Cheng, Kwang-Ting %A Chen, Kuang-Chien %B ASP-DAC %D 1997 %I IEEE %K dblp %P 455-460 %T AQUILA: An equivalence verifier for large sequential circuits. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac1997.html#HuangCC97 %@ 0-7803-3663-1

@inproceedings{conf/aspdac/HuangCC97, added-at = {2017-05-26T00:00:00.000+0200}, author = {Huang, Shi-Yu and Cheng, Kwang-Ting and Chen, Kuang-Chien}, biburl = {https://www.bibsonomy.org/bibtex/28ab7f08fc6bfb16b1cc58c6ab4905c0d/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/1997}, ee = {https://doi.org/10.1109/ASPDAC.1997.600302}, interhash = {7fae3911f7f75fdbcaae9cbfc9cc1fdf}, intrahash = {8ab7f08fc6bfb16b1cc58c6ab4905c0d}, isbn = {0-7803-3663-1}, keywords = {dblp}, pages = {455-460}, publisher = {IEEE}, timestamp = {2019-10-17T16:45:14.000+0200}, title = {AQUILA: An equivalence verifier for large sequential circuits.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac1997.html#HuangCC97}, year = 1997 }