%0 Conference Paper %1 conf/nanonet/VenkataratnamG06 %A Venkataratnam, Aranggan %A Goel, Ashok K. %B Nano-Net %D 2006 %E Maggio, Gian Mario %E Dwyer, Chris %I IEEE %K dblp %P 1-5 %T Design and Simulation of Logic Circuits with Hybrid Architectures of Single Electron Transistors and Conventional Devices. %U http://dblp.uni-trier.de/db/conf/nanonet/nanonet2006.html#VenkataratnamG06 %@ 1-4244-0391-X

@inproceedings{conf/nanonet/VenkataratnamG06, added-at = {2017-05-26T00:00:00.000+0200}, author = {Venkataratnam, Aranggan and Goel, Ashok K.}, biburl = {https://www.bibsonomy.org/bibtex/2c90fc8aef4cc147fe259e317009d7b42/dblp}, booktitle = {Nano-Net}, crossref = {conf/nanonet/2006}, editor = {Maggio, Gian Mario and Dwyer, Chris}, ee = {http://eudl.eu/doi/10.1109/NANONET.2006.346218}, interhash = {819e4d9e222c1615b83baa95e1dd07ae}, intrahash = {c90fc8aef4cc147fe259e317009d7b42}, isbn = {1-4244-0391-X}, keywords = {dblp}, pages = {1-5}, publisher = {IEEE}, timestamp = {2019-10-17T12:57:19.000+0200}, title = {Design and Simulation of Logic Circuits with Hybrid Architectures of Single Electron Transistors and Conventional Devices.}, url = {http://dblp.uni-trier.de/db/conf/nanonet/nanonet2006.html#VenkataratnamG06}, year = 2006 }