%0 Journal Article %1 journals/tvlsi/HuangWZY24 %A Huang, Pengcheng %A Wang, Yaohua %A Zhao, Zhenyu %A Yue, Daheng %D 2024 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 1 %P 137-149 %T CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi32.html#HuangWZY24 %V 32

@article{journals/tvlsi/HuangWZY24, added-at = {2024-01-13T00:00:00.000+0100}, author = {Huang, Pengcheng and Wang, Yaohua and Zhao, Zhenyu and Yue, Daheng}, biburl = {https://www.bibsonomy.org/bibtex/2d6bb2e8749817d5989acc3842ae426e0/dblp}, ee = {https://doi.org/10.1109/TVLSI.2023.3328592}, interhash = {8226fc093bd3c5f598800de903ecdfcb}, intrahash = {d6bb2e8749817d5989acc3842ae426e0}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, month = {January}, number = 1, pages = {137-149}, timestamp = {2024-04-08T14:32:59.000+0200}, title = {CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi32.html#HuangWZY24}, volume = 32, year = 2024 }