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%0 Conference Paper
%1 conf/synasc/Mafteiu-ScaiC16a
%A Mafteiu-Scai, Liviu Octavian
%A Cornigeanu, Calin Alexandru
%B SYNASC
%D 2016
%E Davenport, James H.
%E Negru, Viorel
%E Ida, Tetsuo
%E Jebelean, Tudor
%E Petcu, Dana
%E Watt, Stephen M.
%E Zaharie, Daniela
%I IEEE
%K dblp
%P 424-427
%T A Parallel Heuristic for Bandwidth Reduction Based on Matrix Geometry.
%U http://dblp.uni-trier.de/db/conf/synasc/synasc2016.html#Mafteiu-ScaiC16a
%@ 978-1-5090-5707-8
@inproceedings{conf/synasc/Mafteiu-ScaiC16a,
added-at = {2017-05-19T00:00:00.000+0200},
author = {Mafteiu-Scai, Liviu Octavian and Cornigeanu, Calin Alexandru},
biburl = {https://www.bibsonomy.org/bibtex/2dd7419be6eedc31f0c7c83461c16bfc3/dblp},
booktitle = {SYNASC},
crossref = {conf/synasc/2016},
editor = {Davenport, James H. and Negru, Viorel and Ida, Tetsuo and Jebelean, Tudor and Petcu, Dana and Watt, Stephen M. and Zaharie, Daniela},
ee = {https://doi.org/10.1109/SYNASC.2016.071},
interhash = {82e285c554f4be6a10e6e08b18a8f211},
intrahash = {dd7419be6eedc31f0c7c83461c16bfc3},
isbn = {978-1-5090-5707-8},
keywords = {dblp},
pages = {424-427},
publisher = {IEEE},
timestamp = {2018-11-16T11:38:01.000+0100},
title = {A Parallel Heuristic for Bandwidth Reduction Based on Matrix Geometry.},
url = {http://dblp.uni-trier.de/db/conf/synasc/synasc2016.html#Mafteiu-ScaiC16a},
year = 2016
}